Flyback converter snubber design

  • August 28, 2026
  • 1 hour to complete
  • Workbench v1.9

Introduction

The objective of this experiment is to design a snubber circuit for a flyback converter to clamp the voltage across the switch.

Theoretical background

Unlike the case of an ideal flyback converter waveform discussed in the previous experiment, Flyback converter, the voltage across the transistor of a practical flyback converter has significant ringing due to the parasitic elements.

Flyback converter parasitic transformer leakage inductance and transistor and diode junction capacitance

The energy stored in the transformer leakage inductance and the PCB trace inductance, Ll, unlike the energy stored in the magnetizing inductance Lm, does not transfer over to the secondary side when the transistor is turned off. This energy charges up the transistor’s parasitic capacitance, leading to a high voltage across it, causing significant voltage stress, which can damage the transistor, the transformer insulation, or both.

In a practical flyback converter, the magnitude of the voltage swing is clamped by the use of a snubber circuit.

Flyback converter RCD snubber

The switching cycle waveform of the snubber is shown below. The voltage across the snubber capacitor is assumed to remain constant at Vcs, which is justified given a sufficiently large Cs. At time 0 < t < dTs, when the transistor is on, the primary current increases linearly. During this period, the voltage across the transistor is zero, and there is no current flowing into the snubber circuit because diode Ds is reverse biased with a voltage of Vin + Vcs across it. The snubber capacitor is slowly discharged by the snubber resistor, as shown by the negative current, −VCs / Rs.

Flyback converter RCD snubber waveform showing the input current, transistor voltage, snubber diode voltage, and snubber capacitor current

When the transistor is turned off, the parasitic capacitance across the transistor is charged to the sum of the input voltage and the reflected secondary voltage, Vin + (N1 / N2) × Vo. During this interval, dTs < t < T1, the energy stored in the magnetizing inductance contributes to rapidly charging the transistor’s parasitic capacitance and discharging the secondary-side diode’s junction capacitance. The input current iin remains relatively constant, given the negligible energy transfer from the magnetizing inductance to the parasitic capacitances.

Once the secondary-side diode’s junction capacitance is fully discharged, the diode begins conducting. Simultaneously, the transistor’s parasitic capacitance is charged to Vin + (N1 / N2) × Vo, and the energy stored in the magnetizing inductance starts charging the output capacitor.

During the time interval T1 < t < T2, the snubber diode is still reverse biased since (N1 / N2) × Vo < VCs. The voltage across the transistor continues to rise until it reaches Vin + VCs, plus the diode forward-voltage drop, which is assumed to be negligible, thereby forward biasing the snubber diode. The primary current during this interval falls rapidly because only the energy stored in the primary-side leakage inductance is available to charge the transistor’s parasitic capacitance.

In the absence of the snubber circuit, the energy in the leakage inductance continues to charge the transistor parasitic capacitance, which leads to high voltage ringing across the transistor. In addition to the high voltage, the ringing frequency is typically on the order of megahertz and is a source of significant noise and EMI.

In the presence of the snubber circuit, the primary current flows through the forward-biased snubber diode, charging the snubber capacitor to VCs. VCs remains relatively constant by design, as explained in the following section. During this interval, T2 < t < T3, the primary current continues to fall rapidly. The voltage across the transistor remains clamped at Vin + VCs.

Once the leakage energy is fully transferred to the clamp capacitor at time t = T3, the primary current goes to zero, and the snubber diode gets reverse biased as the transistor voltage drops from Vin + VCs to Vin + (N1 / N2) × Vo.

RCD snubber design

At steady state, since the voltage across the snubber capacitor is constant, the current through the capacitor averaged over a switching cycle is zero.

\[\frac{1}{2} \times I_{\mathrm{pk}} \times (T_{3} - T_{2}) - \frac{V_{\mathrm{Cs}}}{R_{s}} \times T_{s} = 0\tag{1}\]

During the time interval T2 < t < T3, when the snubber diode is forward biased, the voltage across the parasitic inductor Ll is the difference between the voltage across the snubber capacitor and the reflected output voltage across the transformer primary winding.

\[V_{\mathrm{Ll}} = L_{l} \times \frac{\Delta I_{\mathrm{pri}}}{\Delta t} = V_{\mathrm{Cs}} - n \times V_{o}\tag{2}\]

where n = N1 / N2.

The current through the leakage inductor goes from approximately Ipk to zero. The duration of the interval when the snubber diode is conducting can be obtained from Eqn. 2.

\[L_{l} \times \frac{\Delta I_{\mathrm{pri}}}{\Delta t} = L_{l} \times \frac{I_{\mathrm{pk}} - 0}{T_{3} - T_{2}} = V_{\mathrm{Cs}} - n \times V_{o}\]
\[\Rightarrow T_{\mathrm{sn}}= T_{3} - T_{2} = L_{l} \times \frac{I_{\mathrm{pk}}}{V_{\mathrm{Cs}} - n \times V_{o}}\tag{3}\]

The expression for the snubber resistor can be obtained using Eqns. 1 and 3:

\[\frac{1}{2} \times I_{\mathrm{pk}}^{2} \times L_{l} \times \frac{1}{V_{\mathrm{Cs}} - n \times V_{o}} - \frac{V_{\mathrm{Cs}}}{R_{s}} \times T_{s} = 0\]
\[\Rightarrow R_{s} = \frac{V_{\mathrm{Cs}} \times (V_{\mathrm{Cs}} - n \times V_{o})}{0.5 \times I_{\mathrm{pk}}^{2} \times L_{l} \times f_{s}}\tag{4}\]

where fs = 1 / Ts.

Given the converter operating conditions and the desired maximum transistor voltage, the snubber resistor can be determined using the above expression. The lower the tolerable voltage across the transistor, the smaller the snubber resistor and, thus, the higher the losses in the snubber circuit. The power lost in the snubber circuit is:

\[P_{s} = \frac{V_{\mathrm{Cs}}^{2}}{R_{s}} = \frac{1}{2} \times I_{\mathrm{pk}}^{2} \times L_{l} \times f_{s} \times \frac{V_{\mathrm{Cs}}}{V_{\mathrm{Cs}} - n \times V_{o}} = \alpha \times P_{\mathrm{Ll}}\tag{5}\]

where

\[P_{\mathrm{Ll}} = \frac{1}{2} \times I_{\mathrm{pk}}^{2} \times L_{l} \times f_{s}\tag{6}\]
\[\alpha = \frac{V_{\mathrm{Cs}}}{V_{\mathrm{Cs}} - n \times V_{o}}\tag{7}\]

PLl is the leakage-inductor power: the energy stored in the leakage inductor per switching period. α is the factor by which losses in the circuit are scaled due to the presence of the snubber, compared with the circuit without a snubber. Since VCs > (N1 / N2) × Vo, α is always greater than 1. The higher the snubber voltage, the lower the losses, and vice versa.

The value of the snubber capacitor isn’t as crucial as that of the resistor. The only requirement is that the capacitance be large enough to keep the snubber voltage constant. An approximate expression can be obtained from the snubber capacitor current waveform in the above image. Assuming that the current in the snubber resistor is negligible compared to the peak input current Ipk, during the interval when the snubber diode is reverse biased

\[i_{\mathrm{Cs}} = C_{s} \times \frac{\Delta V_{\mathrm{Cs}}}{\Delta t}\]
\[\Rightarrow \frac{V_{\mathrm{Cs}}}{R_{s}} = C_{s} \times \frac{\Delta V_{\mathrm{Cs}}}{T_{s} - T_{\mathrm{sn}}}\]
\[\Rightarrow C_{s} = \frac{1}{R_{s}} \times \frac{V_{\mathrm{Cs}}}{\Delta V_{\mathrm{Cs}}} \times (T_{s} - T_{\mathrm{sn}}) \approx \frac{T_{s}}{R_{s}} \times \frac{V_{\mathrm{Cs}}}{\Delta V_{\mathrm{Cs}}}\tag{8}\]

In the above expression, ∆VCs / VCs is the ratio of the snubber capacitor’s peak-to-peak ripple voltage to its average voltage over a switching cycle. This value is typically chosen between 0.01 and 0.1.

The diode must be a fast-acting diode, such as a Schottky diode, since the conduction period Tsn typically lasts for a short interval.

In the following section, the Flyback converter experiment is repeated, with the only difference being that jumper ❻ on the magnetics card is removed to disconnect the snubber. This will lead to significant ringing in the voltage across the transistor. The results are compared with those obtained in the previous experiment with the snubber connected.

Preparing the Workbench model

  1. Copy the folder containing the pre-built example project for this experiment, usually located at C:\Program Files (x86)\Sciamble\WorkBench v1\Examples\CUSPLab\BasicPowerElectronics\Experiment12, and paste it in a location where the user has permission to edit and save files, such as the Desktop folder.

  2. Launch the Workbench application.

  3. Pin (Dock hide icon) the Explorer dock on the right and the Toolbox dock on the left.

  4. Click the second icon within the Explorer dock, Open simulation/real-time control project button to open the project.

  5. Navigate to the folder where the pre-built example project was pasted in Step 1. Double-click the FlybackConverter_Si.project node within that folder to open the project.

  6. Click the Project expand button icon to explore the files within the project. Double-click the Workbench model logo Flyback node in the Explorer dock to display the model file.

  7. Ensure that the switching frequency is set to 200 kHz. To do this, double-click the project node, Workbench project logo FlybackConverter_Si, in the Explorer. Go to the next page by clicking the Property class next page icon icon in the property dock or choosing Device configuration from the drop-down menu. Check that the Frequency within PWM Configuration is set to 200000.

  8. Ensure that the PWM channel is set to the Si power pole. To do this, open the properties of the tool labeled Si PWM in the model by double-clicking it. Check that the Channel is set to 2.

  9. Open the Slider property and verify that its minimum, maximum, initial, and step values are 0, 0.6, 0, and 0.01, respectively.

Preparing the setup
    warningWarning

    Before proceeding, ensure that the isolated power supply is powered down and that the USB cable is disconnected.

  1. Magnetics card connection: Replace the existing magnetics card with the Flyback magnetics card, making sure that all six pins are properly aligned and in contact with the power-pole board, adjusting the angle if necessary.

    Prior to connecting the card, ensure that jumper ❻ (●) on the magnetics card is disconnected. This is to disconnect the snubber circuit across the transformer primary to observe the real response of the converter in the absence of the snubber circuit.

    warningWarning

    Never leave the magnetics card unscrewed. If contact is lost while the converter is running, interrupting the inductor current can produce a very high voltage, potentially damaging the converter or creating a safety hazard.

  2. Rheostat setting: Set the slider such that the resistance across the two closest rheostat terminals is 8 Ω.

  3. Power connections:

    1. Connect the I+/I- terminals to the isolated power supply:

      1. DC +ve: ● I+ (Red)

      2. DC −ve: ● I− (Black)

    2. Connect the O+/O- terminals to the rheostat load:

      1. Rheostat rail: ● O+ (Red)

      2. Rheostat terminal closest to the rail: ● O− (Black)

    3. Connect the power supply ground to the ground terminal on the board:

      Ground: ● GND (Green)

  4. DSO connections:

    1. Connect DSO channel 1 probe to Ii. Set the following options, if they are supported by the DSO:

      1. Set the probe to 1x.

      2. Set the measurement type as Current.

      3. Set the scaling factor to 4x.

      4. Set the offset at 6 A.

      5. Set termination to 1 MHz.

      6. Set the channel as inverted.

    2. Connect DSO channel 2 probe to Io. Use the same settings as Channel 1.

    3. Connect DSO channel 3 probe to Vo. Set the following options, if they are supported by the DSO:

      1. Set the probe to 1x.

      2. Set the measurement type as Voltage.

      3. Set the scaling factor to 1x.

      4. Set the offset at 0 V.

      5. Set termination to 1 MHz.

      6. Set the channel as default/non-inverted.

    4. Connect DSO channel 4 probe to Sa. Use the same settings as Channel 3.

  5. Jumper settings:

    1. Insert jumpers ❶ and ❺ (●) to bypass the external current-measurement resistors.

    2. Insert jumper ❷ (●) between Sa and Sw. This connects the Flyback magnetics card to the midpoint of the Si power pole.

    3. Jumper ❸ (●) for the GaN FET's external diode may remain inserted or removed, since this experiment does not use the GaN power pole.

    4. Remove jumper ❹ (●) so that the high-side switch does not clamp the flyback switch-node voltage to the positive DC bus.

    5. Remove jumper ❻ (●) on the Flyback magnetics card to disconnect the RCD snubber.

  6. Connect the USB cable to the power-pole board and the computer.

  7. DC power supply settings:

    1. Make sure that the DC power supply is fully turned down to 0 V prior to turning on the supply.

    2. Turn on the power supply and gradually ramp up the voltage from 0 V to 15 V.

    3. If the option is available, set the power supply current limit at 4.5 A.

The final wiring should look similar to this:

Flyback converter wiring diagram

warningWarning

The input and output of a typical flyback converter are galvanically isolated. That is not the case in this lab kit. To enable both external measurement and measurement by the controller of the input, output, and switch voltages without separate isolated probes, the output negative is internally connected to the input negative. Thus the output is not electrically isolated. This does not alter the response of the converter in any manner.

Real-time open-loop control of flyback converter - without snubber
Running the setup:

  1. Click on the Numerical simulation to Real-time mode transition button icon in the top dock of Workbench to transition from the simulation mode to the real-time mode.

  2. Click Numerical simulation and real-time prototyping Run button to run the control algorithm in real time.

  3. If an undervoltage fault occurs, slightly increase the input voltage above 15 V but less than 16 V. Stop the model by clicking on Numerical simulation and real-time prototyping Stop button and rerun it.

  4. Gradually increment the duty cycle from 0 to 0.4 in steps of 0.05. If a fault occurs, stop the model by clicking the Numerical simulation and real-time prototyping Stop button button.

  5. Make the following measurements:

    1. Observe the DSO waveforms and make a copy of the voltage across the switch (channel 4), the output voltage (channel 3), the input/primary current (channel 1), and the diode/secondary current (channel 2) for a duty cycle of 0.4 (or the highest possible value before a fault occurred). Adjust the time base to show between 4 and 10 switching cycles.

      warningWarning

      Do not exceed a duty cycle of 0.5. Even though the input and output voltages, which are monitored by the controller, will be within safe limits, the switch voltage, which is not monitored by the controller, could exceed the device rating at duty cycles greater than 0.5. This is because the voltage across the switch is the sum of the input voltage and the reflected output voltage. In addition, the absence of the snubber circuit leads to significant ringing causing even higher voltage stress across the transistor.

  6. Click on Numerical simulation and real-time prototyping Stop button to stop the model.

Lab report and reading assignment

  1. Attach the DSO waveforms showing the voltage across the transistor, the output voltage, the secondary current, and the primary current for a switching frequency of 200 kHz and a duty cycle of 0.4.

  2. Compare the results obtained with the snubber (previous experiment) and without the snubber (current experiment).

  3. Design an RCD snubber for the flyback converter using the operating conditions and parameters determined in the previous experiment. Assume that the snubber diode is ideal and the peak input current is Ipk = 2 A. The voltage across the transistor should not exceed 35 V under the given operating conditions.

Reference

  1. "Power Electronics, A First Course," Ned Mohan and Siddharth Raju, Wiley Publication.



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